A configurable acquisition
and processing board.
A Zynq MPSoC carrier with four Cortex-A53 cores, two Cortex-R5F cores and 256,000 cells of programmable logic. The converters sit on an FMC mezzanine, either a four-channel ADC card (a custom sixteen-channel card at 14-bit and 100 MSa/s is also available) or a four-channel DAC card. Channel functions and on-board processing are set in firmware, so one board covers applications that would otherwise need several instruments.
What is on the board
A Zynq MPSoC with four Arm Cortex-A53 application cores, two Cortex-R5F real-time cores and 256,000 cells of programmable logic. The converters are not on the carrier: they arrive on an FMC mezzanine, either a four-channel ADC card (a custom sixteen-channel card at 14-bit and 100 MSa/s is also available) or a four-channel DAC card, up to 16-bit and up to 500 MSa/s per channel, behind 80 MHz of analog bandwidth. On the carrier itself there is a separate eight-channel, 18-bit, 2 MSa/s simultaneous-sampling set for slow precision signals, and clocking is a Si5332 at 0–250 MHz with external sync.
Because the front end is a mezzanine, a different converter set or analog conditioning stage is a new daughter card rather than a new carrier board. The digital side stays the same; the front end changes.
Processing runs on the board. In the gamma-ray configuration the trapezoidal filter, peak detection and data analysis occupy a fraction of the programmable logic; the remainder is available to the application, for analysis or for a control algorithm running alongside the acquisition.
Data leaves over Gigabit Ethernet or SFP after processing rather than before it, so event rate is set by the acquisition chain rather than by link bandwidth or host speed.
Firmware defines the instrument
The same board has run gamma-ray pulse-height analysis at TIFR Mumbai and has been benchmarked as a lock-in amplifier on a THz time-domain bench at IISER Kolkata. No hardware differs between the two configurations.
Channel assignment, filter parameters and the processing chain are all firmware. The trapezoidal filter's rise time k and flat-top widthm, for instance, are set per detector and count rate rather than fixed at manufacture.
What the board is configured as
Each configuration below runs on the same carrier board. Channel functions and the processing behind them are set in firmware; where an application needs a different analog front end, it arrives as an FMC daughter card.
Four input channels (a custom sixteen-channel card at 14-bit and 100 MSa/s is also available). Digitise a waveform, or timestamp an edge. Up to 16-bit and up to 500 MSa/s per channel, with 80 MHz of analog bandwidth in front of them.
Four output channels. Drive a level, or play a waveform, phase-locked across boards from the same clock.
One mezzanine per carrier, so a board is four input channels or four output channels rather than both. Resolution and sample rate trade against one another, so 16-bit and 500 MSa/s are not available together; the board is supplied as a set of defined configurations rather than a free choice of all three.
Digitiser
Up to 16 ch · up to 16-bit · up to 500 MSa/s · 80 MHz bandwidth
Precision set: 8 ch · 18-bit · 2 MSa/s · simultaneous sampling
Streaming and triggered capture, with filtering and decimation on the board.
Read moreShow less
The 18-bit precision set sits alongside the fast channels rather than instead of them, for signals that need resolution rather than rate. As an example of the fast path, the gamma-ray configuration runs pulse-height analysis on the board: a trapezoidal filter with rise time k and flat top m set in firmware, then peak detection and data analysis in programmable logic, at 14-bit and 100 MSa/s with no analog shaping amplifier in the chain.
Lock-in amplifier
Sensitivity: pA current · nV voltage
>120 dB dynamic range · 10 MHz or 300 kHz bandwidth
A digital lock-in: phase-sensitive detection of a modulated signal against a reference, with the output low-pass filtered.
Time-to-digital converter
Up to 20 ps timing resolution
Event timing and coincidence measurement, sharing the clock and trigger network with every other channel on the board.
Arbitrary waveform generator
4 ch · up to 16-bit · up to 500 MSa/s
Stimulus and calibration waveforms, with outputs phase-locked across boards.
Inference engine
In designPulse-shape classification and background rejection in logic, applied to samples before they leave the board.
Compute node
In designData carried between boards over the existing high-speed links, so an adjacent board adds processing rather than only channels.
Analysis on the instrument
The Cortex-A53 cores run Linux, so analysis code runs on the board rather than on a host. Programmable logic handles the per-sample work at the sample rate: filtering, peak detection and data analysis. Python handles the per-result work: fitting, calibration, run selection.
Because that code runs on the same board as the acquisition logic, it can change the stimulus or the trigger condition between shots. That allows adaptive measurement rather than selection during analysis.
Inference in the acquisition path
An inference block in the same programmable logic as the acquisition pipeline, operating on samples before they leave the board rather than on a host downstream of it.
Intended uses: pulse-shape classification, background rejection at the microsecond scale, and control loops driven by an inferred quantity rather than a fixed threshold.
The effect is a reduction in recorded data, with selection at acquisition time instead of during analysis, which matters where the data rate rather than the channel count is the constraint. No inference firmware ships today.
Scaling across boards
Boards share a clock and trigger backplane, which scales channel count while preserving phase coherence between them. Carrying data as well as timing over the same links is in design; scheduling several boards as one instrument is not implemented.
One board
Four converter channels, an FPGA, and a quad-core processor. It digitises, filters and analyses data without a host.
Boards synchronised
A shared clock and trigger backplane keeps every board phase-coherent, so channel count grows without losing timing.
Boards sharing data
Data as well as timing over the same links, so an adjacent board adds processing rather than only channels.
One instrument
Multiple boards scheduled as one instrument, with acquisition and processing in the same rack.
Processing scales with channel count
A four-board system is sixty-four converter channels. It is also sixteen Cortex-A53 cores, eight real-time cores and roughly one million cells of programmable logic, positioned behind the converters rather than at the far end of a link.
Where the data rate rather than the channel count is the limiting factor, that ratio of processing to acquisition is the number worth comparing against a conventional digitiser feeding a host.
Tell us what you need to measure
Send the signal levels, sample rates and channel counts your measurement needs. We will say which configuration fits it, whether it is a firmware change, or whether it is outside what this hardware can do.
Describe your measurement